With the explosion of wireless and portable electronic devices, some designers want to dramatically reduce the active and standby power consumption to extend battery life on many Bluetooth and 802.11b devices, as well as mobile devices such as cell phones, hearing aids, Personal Digital Assistants, or laptops. All of these devices use some memory and logic circuits.
Some T-cell based ROM memory array architectures suffer from problems such as 1) bit line coupling due to bit lines running very close to each other, 2) sub-threshold leakage in the memory array for unselected bit cells; and 3) high power consumption when the memory is in standby.
Some ROM memory arrays share source lines between memory columns. However, these ROM Memory arrays have their transistors connected to a permanently grounded source line and may suffer from excess leakage current.
A memory matrix is typically programmed upon fabrication. Generally, in the semiconductor industry, the technical operations implemented in the silicon diffusion layer, Front End, are clearly separated from the operations relative to forming metallizations and vias on the Back End. These two types of operations are performed in different sections of a same array, or even in different array.
From a practical point of view, the logic on a chip for a processor, a memory, or similar component can be prefabricated in the silicon of a diffusion layer. The steps of programming a memory array to determine the logic stored in the ROM may occur in the Back End steps. Thus, an intermediary component can be prefabricated which includes the level of the memory array, a processor, as well as other components implemented in the same integrated circuit. Upon arrival of a customer order, the logic state may be programmed into the ROM array by the metallizations, which enables much faster supply times.